The present invention relates to a semiconductor device with a gate protecting function.
In a semiconductor device employing a MOS transistor for a switching element at the input/output section, switching is performed by changing the voltage at the gate. When the input/output section is formed of a MOS transistor, the gate of the MOS transistor is directly connected to the external terminal. Because of such a structure, if a large noise such as surge voltage is applied to the external terminal, the gate is often destroyed. To prevent the destruction of the gate, an input protection circuit is provided at the input terminal side for receiving an external input signal. This approach, however, is accompanied by a reduction in integration density and an increase in manufacturing cost.
A conventional dynamic RAM (random access memory) has a double layered electrode structure, as shown in FIG. 1. In FIG. 1, an island cell region 3 is formed on the major surface region of a P conductivity silicon substrate 1, while being isolated from other island cell regions (not shown). Formed on the cell region 3 is a thin oxide film 5. The oxide film 5 is in contact with the field oxide film 2. A capacitor electrode 4 made of polycrystal silicon, extending from the oxide film 5 to the field oxide film 2, is formed on the oxide film 5 and the field oxide film 2. An N.sup.- diffusion layer 6 is formed in a cell region 3 under the capacitor electrode 4. An N.sup.+ diffusion layer 7 is also formed in the cell region 3, while remaining separated at a predetermined distance from the N.sup.- diffusion layer 6. In the figure, reference numeral 8 designates a transfer gate electrode made of polycrystal silicon, for example. A gate electrode 8 is provided partially located in the cell region 3 between the N.sup.- diffusion layer 6 and the N.sup.+ diffusion layer 7 through a gate oxide film 9. The gate electrode 8 further partially covers an oxide film 10 layered over the capacitor electrode 4. An interlayer insulating film 11 is formed over the entire surface of the product including a transfer gate electrode 8. An Al (aluminum) interconnection 12 and another Al interconnection 13 are respectively formed through contact holes of the interlayer insulating film 11. The interconnection 12 is physically in contact with the capacitor electrode 4, and the interconnection 13 as a word line is physically in contact with the transfer gate electrode 8.
In the above-mentioned dynamic RAM, by applying voltage through the Al interconnection 13 to the transfer gate electrode 8, a charge transfer is caused between the N.sup.- diffusion layer 6 under the capacitor electrode 4 and the N.sup.+ diffusion layer 7. When an excessively large noise such as surge voltage is applied to the Al interconnection 13, the gate can be destroyed. A measure taken for protecting the gate from this large noise is the provision of an input protecting circuit on the Al interconnection side, as in the semiconductor device where the MOS transistor is provided in the input/output section. This measure, however, is still defective in that the addition of the input protecting circuit reduces integration density and increases the cost of the product.
The double layered electrode structure of the prior dynamic RAM increases the area of the cell region. This is one of the major hindrances in improving integration density. This structure naturally provides a very rugged surface which makes it difficult to form a micropattern. Furthermore, the prior semiconductor device requires the formation of two Al interconnection layers, one for the word line and the other for the bit line. This makes the circuit pattern more complicated.